1. Field of the Invention
This invention relates to operation of Content Addressable Memory (CAM) and particularly to search-line activation for improved performance and reducing noise.
2. Background
Content Addressable Memory (CAM) is an application specific memory designed to accelerate the search of large look-up tables. CAM is commonly used for applications such as address translation in network routers. TLBs, in processor caches, pattern recognition, and data compression. CAM is an attractive solution for these applications because it performs a fully parallel search of the entire look-up table, and, regardless of table size, returns a search result in nanoseconds. FIG. 1 shows a simple CAM architecture that illustrates how this fast search operation is performed. During the search operation the search data in the Search Word Register is supplied to every CAM word via Search-Lines (SLs), compared to every stored word in every entry, and the results of this comparison are displayed on all Match-Lines (MLs). Since both SLs and MLs are highly capacitive and they switch near simultaneously, the CAM search operation not only causes high power consumption but also generates severe on-chip power supply noise in the form of VDD droop and GND bounce. This power-supply noise is especially of concern in Embedded CAM (eCAM), which shares its environment with noise-sensitive circuits. The large supply voltage compression can not only cause failure in the CAM but also affect the neighboring circuits that may be noise-sensitive. Technology scaling further aggravates this problem by decreasing voltage headroom while increasing both current density, which exacerbates the resistive voltage drop, and transition speed, which enlarges Ldi/dt noise.
To reduce CAM induced on-chip noise the switching of the highly capacitive SLs and MLs needs to be spread over a larger time across the cycle, thereby reducing the noise superposition associated with near-simultaneous switching. The conventional search operation first switches the highly capacitive SLs and then activates the ML sensing circuits at the arrival of each active clock. These synchronous switching crowds the SL and ML switching events, superimposing their voltage compression and creating a single large noise event during the search cycle. At the same time the need for faster CAMs is increasing both the peak current demand and reducing the time between the SL and ML switching events.
A need exists, therefore, for an apparatus and method for a low-noise CAM which can improve CAM performance while reducing the voltage compression associated with SL and ML switching A recent development of a new search scheme (precharge-to-GND Match-line sensing scheme is described in U.S. Pat. No. 6,373,738 which is hereby incorporated in its entirety herein) has not only improved power but also enabled new ways of improving sense speed and reducing noise.